IBM unveils new 'Quantum Nighthawk' 120-qubit processor and software stack — company on track for 2029 fault-tolerance milestone

IBM has detailed its most significant quantum computing advances to date, revealing new hardware and software designed to push the limits of what today’s superconducting qubits can do. The announcements, made during IBM’s Quantum Developer Conference on November 12, include a new 120-qubit chip, updates to the Qiskit software stack, and a testbed architecture for running quantum error correction in hardware. Together, the new tools represent a serious step forward on the path to fault-tolerant quantum computing.

Nighthawk expands IBM’s hardware

At the center of IBM’s near-term roadmap is the Nighthawk chip, a 120-qubit superconducting processor built to execute deeper circuits more efficiently than its predecessors. The chip moves away from IBM’s earlier “heavy-hex” qubit layout and instead uses a dense square lattice design. Each qubit connects to four neighbors via tunable couplers, for a total of 218 coupler pairs. That marks a 20% increase in inter-qubit connections over IBM’s Heron chip and reduces the number of swap gates needed to implement complex entangling operations.

IBM says this increase in qubit connectivity directly translates into larger algorithmic workloads. According to IBM, Nighthawk will support circuits with 30% greater complexity than Heron while maintaining comparable fidelity. That estimate is based on live metrics from Heron-class machines already deployed in IBM’s quantum cloud, which recently achieved two-qubit gate fidelities above 99.9% for over 50% of the tested pairs. In benchmarking terms, the chip family reached 330,000 circuit layer operations per second (CLOPS), a 65% gain over its 2024 performance. IBM expects similar or better numbers from Nighthawk once it becomes available to the public.

The new processor will play a central role in IBM’s campaign to demonstrate a verified quantum advantage, which the company now says it expects to achieve by the end of 2026. To support that claim, it has backed the formation of an open “quantum advantage tracker,” inviting third-party researchers to test candidate workloads against classical baselines. Early example circuits from partners, including Algorithmiq and the Flatiron Institute, have already been submitted, focusing on observable estimation and constrained optimization problems.

IBM’s timeline includes further performance gains beyond the current 5,000-gate target. The company expects iterative improvements to push that figure to 7,500 gates in 2026 and 10,000 by 2027, without increasing qubit count. These are incremental steps, but they align with the broader strategy IBM has laid out for gradually improving fidelity and circuit depth while using real benchmarks to validate progress against classical solvers.

Loon lays the groundwork for fault-tolerance

While Nighthawk represents IBM’s best shot at a near-term quantum advantage, the company’s ambitions rest on a longer arc toward fault-tolerant quantum systems. IBM’s engineers believe they’ll get there by the end of the decade, and this week’s preview of the “IBM Quantum Loon” test chip hints at what that system might look like.

Loon is a proof-of-concept superconducting test chip built to validate the hardware components required for scalable quantum error correction. IBM says the processor will include architectural features such as long-range inter-qubit couplers — known as “C-couplers” — designed to enable the efficient implementation of quantum low-density parity-check (qLDPC) codes.

IBM has previously demonstrated its ability to achieve 6-way qubit connections, increase layers of routing on the chip surface, and build reset gadgets that reset the qubit to ground state. “With Loon, for the first time, we test all these features together, aided by new electronic design automation (EDA) to realize more complex architectures than ever before,” says Ryan Mandelbaum, Editor in Chief of IBM Quantum.

On the control side, IBM also announced that its latest classical decoder design, implemented on an AMD FPGA, can process error syndromes in under 480 nanoseconds. That performance is roughly ten times faster than previous iterations and meets the latency threshold required for practical error correction on superconducting hardware. The company says this milestone was reached a year ahead of schedule and will form the basis of future real-time decoding logic for larger fault-tolerant systems.

IBM’s hardware roadmap calls for a series of increasingly modular systems starting in 2026. That includes “Kookaburra,” the company’s first prototype for logical qubit storage, and “Cockatoo,” a 2027 multi-chip device intended to demonstrate entanglement between separate processors. By 2029, the company expects to ship “Starling,” a 1,000-qubit system with 200 error-corrected logical qubits capable of performing more than 100 million operations per job.

Software stack matures further

In parallel with its hardware roadmap, IBM has continued expanding its Qiskit software stack to support more advanced compilation, error mitigation, and classical integration. The latest version, Qiskit 2.2, includes several technical improvements that appear designed to close the gap between theoretical algorithm design and practical execution on real hardware.

Key among those features is full support for dynamic circuits, which allow quantum programs to include mid-circuit measurements and conditional operations based on real-time results. At the conference, IBM demonstrated dynamic circuit execution involving more than 100 qubits, with real-time feedback operations and idle qubit stabilization through pulse-based techniques. According to the company, these methods produced a 25% improvement in output accuracy compared to static circuits, while reducing total gate count by over 50%.

IBM also introduced a new Qiskit tool called Samplomatic, which allows users to add custom annotations to specific regions of a quantum circuit. These annotations are compiled into templates and a new object called the samplex, which defines semantics for circuit randomization. Samplomatic integrates with a new executor primitive to enable composable and efficient error mitigation. According to IBM, applying these techniques in combination with tools like propagated noise absorption and shaded light cones allowed developers to reduce the sampling overhead of probabilistic error cancellation by a factor of 100.

IBM’s latest quantum computing updates reflect a deliberate strategy that balances incremental improvements with long-term architectural goals. The company is not alone in its pursuit of fault tolerance — Google, Intel, and IonQ have laid out their own paths to scale — but IBM’s approach is unusually comprehensive, combining chip design, fabrication, software, and system-level integration under a single roadmap.

Whether the company can hit its 2026 goal remains to be seen. Verified advantage is still a high bar, and the best classical algorithms continue to improve. But Nighthawk appears to offer a legitimate increase in accessible circuit complexity, and IBM’s move to open benchmarking suggests it is willing to let independent comparisons define that moment. On the other side of the equation, Loon offers a credible early platform for testing the essential components of fault-tolerant logic.

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