Intel details progress on fabbing 2D transistors a few atoms thick in standard high volume fab production environment — chipmaker outlines 300-mm fab compatible with integration of 2D transistor contacts and gate stacks

1 week ago 7
Intel
(Image credit: Intel)

2D transistors based on 2D materials have been demonstrated in academia and research labs for more than a decade, but none of these demonstrations were compatible with high-volume semiconductor manufacturing, as they relied on small wafers, custom research tools, and fragile process steps. But this week, Intel Foundry and imec demonstrated a 300-millimeter–ready integration of critical process modules for 2D field-effect transistors (2DFETs), indicating that 2D materials and 2DFETs are moving closer to reality.

Modern leading-edge logic process technologies — such as Intel's 18A, Samsung SF3E, TSMC's N2 — rely on gate-all-around (GAA) devices, and all leading chipmakers are also developing complementary FETs (CFETs) to vertically stack transistors to extend density gains beyond what is possible with GAA. CFETs are considered the next step beyond gate-all-around transistors and are expected to emerge in the next decade. However, Intel and other chipmakers argue that continued scaling will eventually push silicon channels to their physical limits, where electrostatic control and carrier mobility degrade due to extremely small dimensions. To address this, the industry is increasingly evaluating 2D materials, which can form channels only a few atoms thick while maintaining strong current control.

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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

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