'Diamond blanket' transistor cooling method delivers incredible success in testing, drops temps by 70C — micrometer-scale diamond layer grown directly on transistors reduces heat by 90%

A research team at Stanford University has engineered a new approach to handling the thermal bottleneck of RF transistor by using diamonds. By wrapping transistors in an integrated diamond layer, grown on the transistor, researchers were able to decrease chip temperatures by up to 70°C in the real world, and by 90% in simulated tests.

As published in IEEE Spectrum this week, tests using the new diamond method have proven promising leads in the war against thermal bottlenecks in our electronics. As semiconductors and processors grow ever more powerful and dense, the transistors get ever more tightly packed; for instance, Nvidia's Blackwell GPU architecture holds 208 billion transistors on a single GPU.

All this cramming and shrinking is pushing up against thermal constraints, as innovations in efficiency become counteracted by thermal limits. To this end, Stanford researchers led by Srabanti Chowdhury have been studying the use of diamond layers in transistor fabrication for years, since at least 2022.

The use of diamonds in conjunction with GaN transistors is nothing new; Japan also published research on the topic in 2022, and the U.S.'s DARPA fund hired Raytheon to research the topic in 2024. The biggest innovation achieved by Professor Chowdhury's team this week was the ability to grow diamonds directly on semiconductor devices at a low enough temperature to keep the components alive. Before this breakthrough, diamond sheets at the micrometer scale could only be grown in the range of 1,000 degrees Celsius or higher.

Chowdhury and the team's diamond-growing method is able to produce "large-grained polycrystalline diamond all around devices at 400°C." Every word in this quote represents a breakthrough all its own. By adding oxygen to the mix at higher levels than the old methods, non-diamond carbon deposits are etched away, avoiding soot that harms rather than helps conductivity. This 400C temperature is within a survivable range for CMOS devices, while still burning hot enough to create diamonds rather than more soot. The large crystals are also a major part of this method, as producing larger crystals also ensures higher conductivity than a layer of many short crystals sitting next to each other, not spreading heat in a productive manner.

Diamond has been fingered as a component in future chips for years, due to its insanely high thermal conductivity, with single-crystalline diamond measuring six times more conductive than copper. And sourcing and fabbing diamond transistors, while attractive, would be impossible due to the lack of supply in this form factor.

So instead, diamond has become a new component on top of gallium nitride transistors, being grown directly atop semiconductors and forming a silicon carbide interlayer to achieve revolutionary levels of thermal dissipation directly on the transistor. Standard heatsinks on top of semiconductors will never be able to penetrate into a chip to pull heat away from hot spots, especially as 3D chip architectures continue to progress and expand upwards. But a diamond layer surrounding the 3D transistor can seemingly do the job swimmingly.

The Stanford University team is moving forward with industry integration of the diamond conductivity layer. The Pentagon's DARPA program has seemingly wrapped the researchers into its existing GaN transistor diamond project, with results expected in 2027. Beyond defense contracting deals, Stanford also expects to leverage its industry connections with TSMC, Micron, and Samsung to further develop the technology for commercial benefit.

Chipmaking will certainly need to take big swings like this one to survive into the 1nm and smaller era, as fundamental limits of conductivity and heat start mounting exponentially before the transition beyond silicon computing arrives. Time will tell whether printing diamonds on semiconductors can become a stopgap before the end of the silicon era, or even help pave the way to future substrates.

Follow Tom's Hardware on Google News, or add us as a preferred source, to get our latest news, analysis, & reviews in your feeds.